1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and in particular to a configuration generating an optimal voltage in accordance with variation of process conditions.
2. Description of the Background Art
In order to reduce the power consumption of a semiconductor integrated circuit device, it is effective to lower an operating power-supply voltage. This is because, when the operating power-supply voltage is lowered, charging/discharging current of a load capacitance is reduced by the amount of the reduction of the voltage. Thus, as the power-supply voltage is lowered, the power consumption is reduced in proportional to the square of the reduction rate of the voltage.
For example, in a widely-used general-purpose memory, the gate length of a transistor is scaled down to near the limit of micro-fabrication, and an internal power potential of a memory is down-converted by an on-chip voltage down converter while a general-purpose LSI (Large Scale Integration) and an external power-supply voltage are kept equal to each other. This can realize high reliability and low power consumption. Further, by the voltage down converter, a constant internal power potential can also be obtained, and hence a stable operation can be realized without being affected by variation of the external power-supply voltage.
A conventional voltage down converter is now described with reference to FIG. 16. Sub-voltage down converter shown in FIG. 16 includes a constant-current generating circuit 3, a reference voltage generating circuit 4A and a current mirror amplifier 5.
Constant-current generating circuit 3 generates a signal ICONST and a signal BIAS. Constant-current generating circuit 3 generates a stable internal voltage compared to an external voltage, and yet has a circuit configuration capable for keeping a temperature variation of the system to be minimum. Constant-current generating circuit 3 includes transistors TrP-1, TrP-2, TrN-1 and TrN-2, and a resistor Rt. Transistors TrP-1 and TrP-2 are PMOS transistors, whereas transistors TrN-1 and TrN-2 are NMOS transistors.
Transistor TrP-1 is connected between a power-supply voltage and a node ICONST. Resistor Rt and transistor TrP-2 are connected in series between the power supply voltage and node BIAS. The respective gates of transistors TrP-1 and TrP-2 are connected to node ICONST. Transistor TrN-1 is connected between node ICONST and a ground voltage, and transistor TrN-2 are connected between node BIAS and a ground voltage. The respective gates of transistors TrN-1 and TrN-2 are connected to node BIAS. A signal ICONST is output from node ICONST, and a signal BIAS is output from node BIAS.
Transistors TrN-1 and TrN-2 are formed as transistors having the same size and either of the gates is connected to node BIAS, such that the same current I flows on the transistors TrP-1 and TrN-1 side, and the transistors TrP-2 and TrN-2 side.
Transistors TrP-1 and TrP-2 are formed to have the gate lengths L equal to each other and the gate widths W with a ratio of 1:10. A voltage difference xcex94V which is made upon a voltage drop, generated when the same current flows in both transistors, is converted into current I (=xcex94V/Rt). Because resistance Rt requires a large value on the order of several hundred kxcexa9, an interconnection resistance obtained by adjusting the length of gate interconnection materials of the transistor may be used.
Transistors TrP-1 and TrP-3 are formed to have the same size, so that current I is transmitted to the reference voltage generating circuit. At the same time, feed back is provided for the current flowing at transistors TrP-1 and TrP-1 side and at transistors TrP-2 and TrN-2 side. This feed back effect enables the system to transfer an optimal constant current I to the reference voltage generating circuit while monitoring the state of output all the time.
Reference voltage generating circuit 4A includes transistors TrC-1 to TrC-5, TrP-3, and TrP-4. Transistor TrP-3 is connected between a power-supply voltage and a node Vref outputting a reference voltage Vref, and receives signal ICONST at the gate thereof Transistors TrC-5, TrC-1, TrC-2, TrC-3 and TrC-4 are connected in series between node Vref and a node Z0, the respective gates thereof being grounded. Transistor TrP-4 is connected between node Z0 and a ground potential, the gate thereof being grounded.
Switches SW1 to SW4 are respectively arranged for transistors TrC-1 to TrC-4. When a switch SWi (i=1 to 4) is turned on, the drain and the source of a transistor TrC-i are connected.
A channel resistance including transistors TrC-1 to TrC-4 and TrC-5 are denoted by Rc. (Ixc3x97Rc+Vtp) is output as a reference voltage Vref, which is a sum of a potential difference Ixc3x97Rc at channel resistance Rc receiving current I and a potential difference Vtp, substantially corresponding to a threshold voltage of transistor Trp-4, at transistor TrP-4 generated when current I flows. The threshold of transistor TrP-4 is hereinafter referred to as Vtp.
Current mirror amplifier 5 includes a main amplifier 1 having a large driving power operated when an internal circuit driven by an output Int.Vcc is activated, and a sub-amplifier 2 having a small driving power which is constantly operated.
Main amplifier 1 includes PMOS transistors TrP-10, TrP-11, Ti and T5, and NMOS transistors TrN-3, TrN-10 and TrN-11. Sub-amplifier 2 includes PMOS transistors TrP-10, TrP-11 and T2, and NMOS transistors TrN-3, TrN-10 and TrN-11.
Main amplifier 1 is now described. Transistor TrP-10 is connected between a power-supply voltage and a node COMPA, and transistor TrP-11 is connected between a power-supply voltage and a node Z11, and the respective gates of transistors TrP-10 and TrP-11 are connected to a node Z11.
Transistor TrN-10 is connected between node COMPA and a node Z12, and receives reference voltage Vref at the gate thereof. Transistor TrN-11 is connected between node Z11 and node Z12, and the gate thereof is connected to a node OUT outputting an internal power-supply voltage int.Vcc. Transistor TrN-3 is connected between node Z12 and a ground voltage, and receives an activation signal ACT for making the gate to operate the internal circuit.
Transistor T1 is connected between the power-supply voltage and node COMPA, and receives activation signal ACT at the gate thereof. Transistor T5 is connected between the power-supply voltage and node OUT, and the gate thereof is connected to node COMPA.
Sub-amplifier 2 is now described. A connecting node of transistors TrP-10 and TrP-11 is referred to as a node COMPS. Transistors TrP-10, TrP-11, TrN-10, TrN-11 and TrN-3 are connected as described above. Transistor TrN-3 in sub-amplifier 2 receives signal BIAS output from constant-current generating circuit 3. Transistor T2 is connected between the power-supply voltage and node OUT, and the gate thereof is connected to node COMPS.
An amplifier is an important circuit determining the driving power of the system, and a constant-current generating circuit and a reference voltage generating circuit are greatly important for minimizing variation of an internal potential for a change of a temperature or an external voltage, and are very delicate for changes of various conditions. The properties of the constant-current generating circuit and the reference voltage generating circuit determine the operational property of the system.
In reference voltage generating circuit 4A, channel resistance Rc is formed from a transistor having a long gate length. To generate a desired reference voltage Vref independent of variation in a resistance value for a threshold due to process variation, combinations of on/off of switches SW1 to SW4 can change the value of channel resistance Rc in 16 stages.
If the ratio of the gate length of transistors TrC-1 to TrC-4 is made to be TrC-1: TrC-2: TrC-3: TrC-4=1:2:4:8, voltage tuning in 16 stages can be performed at almost regular intervals. By assuming that the output reference voltage Vref varies between xc2x110-20% for a set value due to a process change, the circuit is made such that the output voltage can be adjusted to the set value as long as the variation is in the above range.
Considering the property of the system, reference voltage Vref desirably has low dependencies on an external voltage and a temperature.
As for the external voltage dependency, resistance Rt, channel resistance Rc and threshold Vtp have potential differences in accordance with constant current I. Therefore, reference voltage Vref tends to have no direct voltage dependency. Further, it should be appreciated the external voltage dependency is low in the first place in the reference voltage generating circuit, since the potential difference xcex94V is independent of a voltage as described above.
The temperature dependency is subsequently described. As for the temperature dependency of each material, when the temperature rises from 27xc2x0 C. to 87xc2x0 C., resistance Rt (gate interconnection material) and channel resistance Rc are increased by approximately 10%, and threshold Vtp is decreased by approximately 10%. Further, because of the temperature dependencies of transistors TrP-1 and TrP-2, the potential difference xcex94V is increased by approximately 20%. Therefore, current I determined by xcex94V/Rt is also increased.
These values are applied, for example, to constant-current generating circuit 3 and reference voltage generating circuit 4A. The tuning steps in 16 stages and on/off of switches SW1 to SW4 in each step have relations shown in FIG. 17.
Assuming that external voltage 3.3V generates a reference voltage 2V. As shown in FIG. 18, a voltage of 1.5V to 2.3V is generated at a room temperature of 27xc2x0 C., whereas a voltage of 1.5V to 2.7V is generated at a high temperature of 100xc2x0 C. This means that an Ixc3x97Rc component is increased as a tuning step goes higher. Thus, it can be seen that a positive temperature dependency is increased.
As an alternative example of a reference voltage generating circuit, a reference voltage generating circuit 4B is shown in FIG. 19. Reference voltage generating circuit 4B includes, in addition to the configuration of reference voltage generating circuit 4A, a PMOS transistor TIP-5. Transistor TrP-5 is connected between transistors TrC-4 and TrP-4. The threshold of transistor TrP-5 is substantially the same as threshold Vtp of transistor TrP-4.
In reference voltage generating circuit 4B, a threshold component of the transistor is made to be 2xc3x97Vtp. The ratio of threshold Vtp with a negative temperature dependency is increased compared to that of the component with positive temperature dependency (Ixc3x97Rc). Therefore, as shown in FIG. 20, no temperature dependency exists near the middle stage of the tuning steps, i.e., near the tuning step 8, either at the room temperature 27xc2x0 C. or the high temperature 100xc2x0 C. However, the positive or negative temperature dependency appears at both ends of the tuning steps (tuning step 1 or 16).
As an alternative example of a reference voltage generating circuit, a reference voltage generating circuit 4C is shown in FIG. 21. Reference voltage generating circuit 4C includes the same components as the ones in reference voltage generating circuit 4B. In reference voltage generating circuit 4C, the respective gates of transistors TrC-1 to TrC-5 are connected to node Z1. Threshold Vtp is input to these gates. This reduces the temperature dependency of channel resistance Rc. Therefore, as shown in FIG. 22, the ratio of threshold Vtp with negative temperature dependency is higher to that of channel resistance Rc.
It is noted that the tuning steps are programmed using a fuse. A switch control circuit controlling switches with the fuse will be described with reference to FIGS. 23 and 24.
Switch control circuit 50 shown in FIG. 23 includes transistors T101 to T103, NAND circuit 11, a fuse 12, inverters 15 and 16, and a logic circuit 14. Transistor T101 is a PMOS transistor, and transistors T102 and T103 are NMOS transistors.
Transistor T101 and fuse 12 are connected in series between a power-supply voltage and a node FIN. Transistors T102 and T103 are connected between node FIN and a ground voltage. Inverter 15 inverts a signal at node FIN. The gate of transistor T102 receives a signal BIAS output from constant-current generating circuit 3, and the gate of transistor T103 receives an output of inverter 15. NAND circuit 11 receives two types of signals, i.e., a signal TSIGn and a tuning signal TUNE. Logic circuit 14, receiving an output of NAND circuit 11 and an output of inverter 16 inverting the output of inverter 15, outputs a control signal MODEn.
A switch SWn receiving an output of switch control circuit 50 is turned on/off in response to control signal MODEn.
A switch control circuit 60 shown in FIG. 24 includes an inverter 17, in addition to the configuration of switch control circuit 50. Inverter 17 inverts the output of logic circuit 14 and outputs a control signal /MODEn. Switch SWn receiving the output of switch control circuit 60 is turned on/off in response to control signal /MODEn.
Tuning signal TUNE is at level L in a normal operational state, and becomes at level H when a tuning mode is activated. Signal TSIGn is a signal for controlling on/off of switch SWn during the tuning mode.
Signal BIAS prevents node FIN from being in a floating state when the fuse is blown off.
Assuming here that the size of transistor T102 receiving signal BIAS at the gate thereof is the same as that of transistors TrN-1 and TrN-2, then current I as same as the one in reference voltage generating circuit 4A will flow due to a current mirror effect.
As described above, current I is a small current represented by I=xcex94V/Rt, and thus node FIN is at level H before fuse 12 is blown off. By contrast, after fuse 12 is blown off, node FIN is driven to level L by signal BIAS, and the value will be latched.
In the normal operational state, where the tuning signal TUNE is L, switch control circuit 50 turns off switch SWn (control signal MODEn is L) if the fuse is not yet blown off. Control signal MODEn will have level H after the fuse is blown off, so that switch SWn is turned on.
In the normal operational state, where tuning signal TUNE is L, switch control circuit 60 turns on switch SWn (control signal /MODEn is H) if the fuse is not yet blown off.
Switch control circuit 50 is arranged for each of switching SWl to SW3 of reference voltage generating circuits 4A to 4C, and switch control circuit 60 is arranged for switch SW4 of reference voltage generating circuits 4A to 4C.
Switch control circuits arranged for switches SW1 to SW4 are denoted by switch control circuits 111 to 114. Switch control circuit 111 receives signals TUNE and TSIG1, and outputs a control signal MODE1. Switch control circuit 112 receives signals TUNE and TSIG2, and outputs control signal MODE2. Switch control circuit 113 receives signals TUNE and TSIG3, and outputs a control signal MODE3. Switch control circuit 114 receives signals TUNE and TSIG4, and outputs a control signal MODE4.
First, such switch control circuits are used to change the voltage levels of control signals by two types of signals, i.e., TSIGn and TUNE, before the fuse is blown off. This can simulate a state where fuse 12 is virtually blown off, to monitor an internal power supply. Based on the monitored result, a dedicated test device is used to blow off the fuse by a laser.
If such a fuse element system is used, the fuse is protected by a guard ring or the like such that polysilicon or the like sputtered by the laser will not adversely affect the other circuits.
Thus, the area of a redundancy circuit programmed by the fuse element system is enlarged. As a design rule is progressed, the rate of the fuse occupied in the chip area has become a problem. A tuning information transfer system transferring tuning information has been developed to solve this problem.
In the tuning information transfer system, as described in Japanese Patent Laid Open No. 11-194838, voltage tuning information is transferred to a chip during a certain period after the power is turned on for a device.
It depends on a specification which of the fuse element system and the tuning information transfer system is used.
In a conventional circuit configuration, a temperature dependency of the reference voltage Vref level may significantly vary when a process variation is caused. Also, when a transition occurs from an initial small-lot production phase to a mass production phase, or when a mass production factory is changed, a constant process parameter may vary. In such a case, a reference voltage generating circuit may possibly show a constant large temperature dependency, and thus a circuit will have to be replaced. However, it is difficult to determine, at a designing stage, which type of the reference voltage generating circuit is optimal.
Therefore, the present invention provides a semiconductor integrated circuit device enabling generation of an optimal reference voltage without replacement of a circuit.
A semiconductor integrated circuit device according to the present invention includes a reference voltage generating circuit configured to be switched to any one of a plurality of circuit configurations having different properties, and generating a reference voltage using any one of the plurality of circuit configurations, and a control circuit for controlling switching of the plurality of circuit configurations.
Preferably, the plurality of circuit configurations include first and second circuit configurations different from each other, or first, second and third circuit configurations different from one another.
Particularly, the control circuit generates a control signal for the switching in response to a test mode, and the reference voltage generating circuit is switched, for tuning, to any one of the plurality of circuit configurations based on the control signal.
Particularly, the control circuit generates a control signal for the switching based on a combination of two exclusive test modes, and the reference voltage generating circuit is switched, for tuning, to any of a plurality of circuit configurations based on the control signal.
Particularly, the control circuit includes a fuse, and generates a control signal for the switching by blowing off the fuse.
Particularly, the control circuit includes a latch circuit, and generates a control signal for the switching based on tuning information held in the latch circuit.
Particularly, the reference voltage includes a first reference voltage and a second reference voltage different from the first reference voltage. The semiconductor integrated circuit device according to the present invention further includes a first buffer receiving the first reference voltage and a second buffer receiving the second reference voltage.
Therefore, according to the semiconductor integrated circuit device, the reference voltage generating circuit can perform an optimal circuit configuration among a plurality of possible circuit configurations, to generate a reference voltage. Thus, even an emergent process variation can be dealt with. A tuning can be performed with an optimal reference voltage generating circuit adapted to a process condition, without a troublesome replacement of circuits.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.